openFPGALoader(1) openFPGALoader(1)

openFPGALoader - flash FPGAs

openFPGALoader [OPTION...] BIT_FILE

Universal utility for programming FPGAs. Compatible with many boards, cables and FPGA from major manufacturers (Xilinx, Altera/Intel, Lattice, Gowin, Efinix, Anlogic, Cologne Chip). openFPGALoader works on Linux, Windows and macOS.

Not sure if your hardware is supported? Check the hardware compatibility lists:

  • https://trabucayre.github.io/openFPGALoader/compatibility/fpga.html
  • https://trabucayre.github.io/openFPGALoader/compatibility/board.html
  • https://trabucayre.github.io/openFPGALoader/compatibility/cable.html

Mandatory or optional arguments to long options are also mandatory or optional for any corresponding short options.

DFU interface altsetting (only for DFU mode)
bitstream
secondary bitstream (some Xilinx UltraScale boards)
board name, may be used instead of cable
disable spiOverJtag model detection by providing bitstream(intel/xilinx)
jtag interface
JTAG mode / FTDI: GPIO pin number to use as a status indicator (active low)
JTAG mode / FTDI: read on negative edge instead of positive
probe Vendor ID
probe Product ID
probe index (FTDI and cmsisDAP)
select a probe by it bus and device number (bus_num:device_addr)
FTDI chip serial number
FTDI chip channel number (channels 0-3 map to A-D)
device to use (/dev/ttyUSBx)
detect FPGA
DFU mode
Dump flash mode
Bulk erase flash
for boards with multiple flash chips (some Xilinx UltraScale boards), select the target flash: primary (default), secondary or both
select ext flash for device with internal and external storage
provides size in Byte to dump, must be used with dump-flash
provides file type instead of let's deduced by using extension
flash sector (Lattice parts only)
fpga model flavor + package
jtag frequency (Hz)
write bitstream in flash (default: false)
device index in JTAG-chain
add JTAG non-FPGA devices <idcode,irlen,name>
IP address (XVC and remote bitbang client)
list all supported boards
list all supported cables
list all supported FPGA
write bitstream in SRAM (default: true)
Start address (in bytes) for read/write into non volatile memory (default: 0)
pin config TDI:TDO:TCK:TMS
firmware for JTAG probe (usbBlasterII)
protect SPI flash area
Produce quiet output (no progress bar)
reset FPGA after operations
scan USB to display connected probes
skip writing bridge to SRAM when in write-flash mode
skip resetting the device when in write-flash mode
SPI mode (only for FTDI in serial mode)
Unprotect flash blocks
Produce verbose output
verbose level -1: quiet, 0: normal, 1:verbose, 2:debug
Give this help list
Verify write operation (SPI Flash only)
Xilinx Virtual Cable Functions
Xilinx Virtual Cable and remote bitbang Port (default 3721)
Microcontroller firmware
Connect JTAG to MCU
Read DNA (Xilinx FPGA only)
Read XADC (Xilinx FPGA only)
Print program version

Report bugs to <gwenhael.goavec-merou@trabucayre.com>.

29 August 2024